Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide systems and methods with timing control for synchronization rectifier controllers. Merely by way of example, some embodiments of the invention have been applied to power converters operating under continuous conduction mode. But it would be recognized that the invention has a much broader range of applicability.
Conventional secondary-side synchronization rectifier (SR) controllers often are used as parts of power conversion systems. These conventional power conversion systems usually need to support multiple modes of operation. The modes of operation include discontinuous conduction mode (DCM), quasi-resonant mode (QR) and continuous conduction mode (CCM).
FIG. 1 is a simplified diagram showing a conventional flyback power conversion system with a conventional secondary-side synchronization rectifier (SR) controller. The power conversion system 100 (e.g., a power converter) includes an electromagnetic interference (EMI) filter 101, a rectifying bridge 102, capacitors 103 and 107, resistors 105 and 106, a diode 109, a primary winding 112, a secondary winding 114, a primary-side pulse-width-modulation (PWM) controller 120 (e.g., a chip), a secondary-side synchronization rectifier (SR) controller 130 (e.g., a chip), a primary-side switch 142 (e.g., a transistor), a secondary-side switch 144 (e.g., a transistor), an output resistive load 152, and an output capacitive load 154.
The primary-side PWM controller 120 generates a drive signal 121. The drive signal 121 is received by the switch 142 (e.g., a transistor) and is used to close or open the switch 142 (e.g., to turn on or off a transistor) to affect a current 141 flowing through the primary winding 112. Additionally, the secondary-side SR controller 130 (e.g., a chip) includes a controller terminal 138 (e.g., a pin) and a controller terminal 139 (e.g., a pin). The secondary-side SR controller 130 receives, at the controller terminal 138, a signal 131 (e.g., Vd) from the drain terminal of the transistor 144 (e.g., a MOSFET transistor), generates a drive signal 137 (e.g., Vg), and outputs, at the controller terminal 139, the drive signal 137 to the transistor 144. The drive signal 137 is received by the gate terminal of the transistor 144 and is used to turn on or off the transistor 144 to affect a current 146 flowing through the secondary winding 114.
As shown in FIG. 1, the secondary-side SR controller 130 includes a drain-voltage detector 132, a logic controller 134, and a gate driver 136. The drain-voltage detector 132 receives the signal 131 (e.g., Vd) from the drain terminal of the transistor 144, detects the received signal 131, and generates a detection signal 133. The detection signal 133 is received by the logic controller 134, which in response generates a control signal 135. The gate driver 136 receives the control signal 135 and outputs the drive signal 137 (e.g., Vg) to the gate terminal of the transistor 144. The drive signal 137 (e.g., Vg) is generated based at least in part on the detected signal 131 (e.g., Vd), and is used to turn on or off the transistor 144. If the drive signal 137 is at a logic high level, the transistor 144 is turned on, and if the drive signal 137 is at a logic low level, the transistor 144 is turned off.
FIG. 2 is a simplified diagram showing certain conventional components of the secondary-side synchronization rectifier controller 130 of the power conversion system 100. The drain-voltage detector 132 includes comparators 210 and 220. The comparator 210 receives the signal 131 (e.g., Vd) and a threshold signal 212 (e.g., Vth_on) and generates a comparison signal 214. The comparator 220 receives the signal 131 (e.g., Vd) and a threshold signal 222 (e.g., Vth_off ) and generates a comparison signal 224. The detection signal 133 includes comparison signals 214 and 224.
As shown in FIGS. 1 and 2, when the power conversion system 100 operates under the DCM mode or the QR mode, the drive signal 137 changes from the logic low level to the logic high level and the transistor 144 changes from being turned off to being turned on, if the detected signal 131 (e.g., Vd) drops below the threshold signal 212 (e.g., Vth_on) and the comparison signal 214 changes from the logic low level to the logic high level. Also, when the power conversion system 100 operates under the DCM mode or the QR mode, the drive signal 137 changes from the logic high level to the logic low level and the transistor 144 changes from being turned on to being turned off, if the detected signal 131 (e.g., Vd) rises above the threshold signal 222 (e.g., Vth_off) and the comparison signal 224 changes from the logic high level to the logic low level.
For example, the threshold signal 222 (e.g., Vth_off) is close to 0 V (e.g., being equal to −15 mV), so the detected signal 131 (e.g., Vd) rises above the threshold signal 222 (e.g., Vth_off) and the comparison signal 224 changes from the logic high level to the logic low level at the end of the demagnetization period when a secondary current 116 that flows through the secondary winding 114 becomes sufficiently small in magnitude. In another example, when the power conversion system 100 operates under the DCM mode or the QR mode, the transistor 144 becomes turned off before the transistor 142 becomes turned on.
For a flyback power conversion system with a secondary-side synchronization rectifier (SR) controller, the accurate control of the timing for opening a secondary-side switch (e.g., turning off a transistor) often is important. Under the CCM mode, however, the control mechanisms as implemented in FIGS. 1 and 2 usually are not applicable. Hence it is highly desirable to improve the techniques related to secondary-side synchronization rectifier controllers.